1. Field of the Invention
This invention relates to a semiconductor device, a manufacturing method thereof, and a data processing system. More particularly, this invention relates to a semiconductor device having wiring lines the surfaces of which are covered with a protecting insulation film, a manufacturing method thereof, and a data processing system including such a semiconductor device.
2. Description of the Related Art
Recent progress in miniaturization of semiconductor devices has made it difficult to form hole patterns solely with photolithography. In cell arrays of a memory product such as a DRAM, in particular, a hole pattern having holes arranged with minimum pitches must be formed in spaces of wiring lines which are arranged also with minimum pitches in a wiring layer, without causing short circuit with the wiring layer. Therefore, the hole size is reduced significantly, which makes it difficult to form the hole pattern only with photolithography.
Conventionally, this problem has been solved by employing a fine hole pattern formation method in which a silicon nitride (SiN) protecting film formed to cover the surface of a wiring layer is used as a mask, and a hole pattern is formed by a selective etching using a slit pattern formed orthogonally to the protecting film. Using the selective etching process, an interlayer insulation film is etched with a high selection ratio to SiN to form slit grooves corresponding to the slit pattern, and the slit grooves are filled with a conductive material. Subsequently, excessive conductive material is removed by CMP (Chemical-Mechanical Polishing) while using, as a stopper, the SiN film covering the surface of the wiring layer, whereby the conductive material is divided into separate via plugs.
According to this method, however, the SiN film functioning as a mask is thinned several times, specifically by the etching for processing the wiring layer, the etching for forming slit grooves, and the polishing by CMP. This makes it difficult to leave the SiN film with a sufficient thickness so as not to expose the wiring layer ultimately. If the initial thickness of the SiN film is increased to ensure the SiN film is left with a sufficient thickness, it becomes difficult to fill the narrow spaces between the wiring layers arranged with a minimum pitch, with the insulation film. This poses a problem that the increased thickness of the SiN film for protecting the wiring lines hampers the miniaturization of the semiconductor device.
Japanese Laid-Open Patent Publication No. 2001-298082 (Patent Document 1) describes a technique for solving the problem above. According to Patent Document 1, a SiN protecting film covering the surface of a wiring layer forming each bit line of a DRAM device is covered with an interlayer insulation film, and an etching stopper film made of NSG (non-silicon glass) is formed all over the surface of the interlayer insulation film. A thick interlayer insulation film for accommodating storage nodes is formed on the etching stopper film. When etching the interlayer insulation film, the etching stopper film prevents the SiN protecting film from being etched away, and hence the reduction of the thickness of the SiN protecting film can be prevented. When the etching of the interlayer insulation film is completed, the etching stopper film is then etched. Further, a self-aligning etching is performed on the bit lines, whereby contact holes are formed to reach a diffusion layer in the silicon substrate. A Si3N4 film for example is used as the etching stopper film.